DCDC=0, LPTMR=0, BTLL=0, TSI=0, ZigBee=0, PHYDIG=0, PORTB=0, PORTA=0, LTC=0, LPUART0=0, PORTC=0
System Clock Gating Control Register 5
LPTMR | Low Power Timer Access Control 0 (0): Access disabled 1 (1): Access enabled |
TSI | TSI Access Control 0 (0): Access disabled 1 (1): Access enabled |
PORTA | Port A Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
PORTB | Port B Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
PORTC | Port C Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
LPUART0 | LPUART0 Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
LTC | LTC Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
RSIM | RSIM Clock Gate Control |
DCDC | DCDC Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
BTLL | BTLL System Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
PHYDIG | PHY Digital Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |
ZigBee | ZigBee Clock Gate Control 0 (0): Clock disabled 1 (1): Clock enabled |